implement virtual memory and caching scheme using Go or C/C++ and least recent used (LRU) replacement algorithm.

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Virtual Memory and Caching (150 points)                                                              

Please implement virtual memory and caching scheme using Go or C/C++ and least recent used (LRU) replacement algorithm. Your program should display cache misses, page misses, and replacement information.

The syntax of the commands are:

wordSize(<size in bits>) # 8, 16, 32, 64 memorySize(<size in KB/MB/GB>) cacheSize(<size in B/KB/MB>) pageSize(<size in B/KB/MB>)

sharedLibrary(<sid>, <memorySpace in KB/MB/GB/TB> process(<pid>, <memorySpace in KB/MB/GB/TB>, [<sid>]) reference(<pid>, <startAddress>, <size in B/KB/MB>) terminate(<pid>)

The wordSize, memorySize, cacheSize, and pageSize should occur exact once in any order and before all the rest commands, and process, reference, and terminate can occur 0 or more times in any order from the input. To make Autotest working, your program reads in commands (any of the above function calls) and executes the commands one after another. The address is input as hex number, and all others are decimal numbers (with optional B/KB/MB/GB/TB unit). The process may contain sharedLibrary in their beginning memorySpace. For any illegal input command, simply print error message and stop. Your program should check size constraints (e.g., pageSize < cacheSize < memorySize < memorySpace = 2wordSize), protect against illegal memory accesses (i.e., print error message, ignore the request, and continue the next command).

 

Example input (and optional output as comments):

# small cpu example wordSize(16) memorySize(16KB) cacheSize(4KB) pageSize(1KB)

 sharedLibrary(1, 64KB) sharedLibrary(2, 64KB) process(11, 32KB, 1)

reference(11, 0x379, 512B) # page 0 & 1 of pid=11

# cache miss, page miss, load page 0 of pid=11 to mem[0], then to cache[0] # cache miss, page miss, load page 1 of pid=11 to mem[1], then to cache[1] process(7, 16KB, 1)

process(17, 16KB, 2)

reference(17, 0x1, 16B) # page 0 of pid=17

# cache miss, page miss, load page 0 of pid=17 to mem[2], then to cache[2] reference(17, 0x10c, 8B) # page 0 of pid=17

reference(7, 0x0, 1024B)   # page 0 of pid=7

# cache miss, page miss, load page 0 of pid=7 to mem[3], then to cache[3] process(73, 64KB, 2)

reference(11, 0x10c, 8B) # page 0 of pid=11 reference(7, 0x8a4e, 8B) # page 34 of pid=7

# cache miss, page miss, load page 34 of pid=7 to mem[4], then to cache[1] reference(73, 0xc, 8B) # page 0 of pid=73

# cache miss, page miss, load page 0 of pid=73 to mem[5], then to cache[2] reference(17, 0xf16, 16B) # page 3 of pid=17

# cache miss, page miss, load page 3 of pid=17 to mem[6], then to cache[3] reference(7, 0x42a, 8B) # page 1 of pid=7

# cache miss, page miss, load page 1 of pid=7 to mem[7], then to cache[0] terminate(73)

terminate(11) terminate(17)

reference(7, 0x100, 256B) # page 0 of pid=7

# cache miss, page hit, load page 0 of pid=7 to cache[2]

 

 

 

 

 

Student Name:

 

SSN/ID:

 

Score:

Correctness and boundary condition (50%):

Whitespace and free format compliance (5%):

Compiling without warning/error (5%):

Error Handling (5%):

Modular design, file/directory organizing, showing input, documentation, coding standards (30%):

Automation (5%):

Subtotal:

Late penalty (20% per day): Special service penalty (5%):

Total score:

 

 

 

Attachments:

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