CS3339 Assignment 4. Assuming an LRU replacement policy and assuming that the LRU bits for each line are saved inside the line, what is the total number of bits required for the entire cache?

INSTRUCTIONS TO CANDIDATES

ANSWER ALL QUESTIONS

Hi there! I need help completing this assignment. I 

 

CS3339 Assignment 4  

Submission Instructions:

Please follow the submission instructions provided in assignment 1.

Additionally, please note that you must show all the details of your work. Submission without sufficient

details will be rejected.

Assignment Instructions:

1. Using the 2-way set associative D-cache depicted below; give the result of the following memory

accesses. These memory accesses are byte references.

a. Write to AE

b. Read from AC

c. Write to B4

d. Read from C7

e. Write to D2

f. Read from F4

g. Write to F7

h. Read from 29

i. Write to 10

j. Read from 2A

• The result should be in the format of ‘H:’ (hit), ‘CM:’ (compulsory miss) or ‘M:’ (miss).

• Use the LRU replacement policy; assuming that 0 denotes LRU and 1 denotes MRU.

• If you replace a block, assume that only the tag is changed and the data (marked as X) is

unchanged.

• All numeric values are in hexadecimal.

2. Consider a direct mapped memory hierarchy with the following specifications: The main

memory is 64K bytes, the block size is 32 bytes, the cache is an I-cache, and it has 32 lines.

Furthermore, initially all the blocks are invalid

For each of the following memory accesses determine whether it is a hit (H), compulsory

miss (C), or non-compulsory miss (M). Explain your answer in sufficient details.

a. PC = CA12________

b. PC = CA13________

c. PC = CA23________

d. PC = CA14________

 e. PC = CA24________

f. PC = FE15________

g. PC = FE13________

h. PC = FE23________

i. PC = FE14________

j. PC = FE24________

Set-0

TAG D0 D1 D2 D3 D4 D5 D6 D7 V D LRU

1010 X X X X X X X X 1 0 0

1011 X X X X X X X X 0 1 1

Set-1

TAG D0 D1 D2 D3 D4 D5 D6 D7 V D LRU

1100 X X X X X X X X 0 1 1

1101 X X X X X X X X 1 0 0

CS3339 Assignment 4 Due 11-28-2021

3. Answer the following questions related to reference addresses:

a. Given a 64-byte cache block, a 32 KB direct-mapped D-cache (assume byte-addressable), and

a 32-bit address reference word, which bits of a reference word would be used for tag, index,

and offset? How many bits per line will be saved in the cache?

b. Given a 128-byte cache block a set associative D-cache with 4 sets and 4 lines per set (assume

byte-addressable), and a 24-bit address reference word, which bits of a reference word would

be used for tag, index, and offset? Assuming an LRU replacement policy and assuming that

the LRU bits for each line are saved inside the line, what is the total number of bits required

for the entire cache?

4. Consider a memory hierarchy with two levels of cache (l1 and l2). The access time to the l1 cache

is 10 nano-seconds, the access time to the l2 cache is 100 nano-seconds, and the access time to

the Main Memory is 1 micro-second. The hit ratio in the l1 cache is 0.85 and the hit ration in the

l2 cache is 0.9. Find the Expected Access time for this configuration.

Attachments:

Expert's Answer

378 Times Downloaded

Related Questions

. Introgramming & Unix Fall 2018, CRN 44882, Oakland University Homework Assignment 6 - Using Arrays and Functions in C

DescriptionIn this final assignment, the students will demonstrate their ability to apply two ma

. The standard path finding involves finding the (shortest) path from an origin to a destination, typically on a map. This is an

Path finding involves finding a path from A to B. Typically we want the path to have certain properties,such as being the shortest or to avoid going t

. Develop a program to emulate a purchase transaction at a retail store. This program will have two classes, a LineItem class and a Transaction class. The LineItem class will represent an individual

Develop a program to emulate a purchase transaction at a retail store. Thisprogram will have two classes, a LineItem class and a Transaction class. Th

. SeaPort Project series For this set of projects for the course, we wish to simulate some of the aspects of a number of Sea Ports. Here are the classes and their instance variables we wish to define:

1 Project 1 Introduction - the SeaPort Project series For this set of projects for the course, we wish to simulate some of the aspects of a number of

. Project 2 Introduction - the SeaPort Project series For this set of projects for the course, we wish to simulate some of the aspects of a number of Sea Ports. Here are the classes and their instance variables we wish to define:

1 Project 2 Introduction - the SeaPort Project series For this set of projects for the course, we wish to simulate some of the aspects of a number of